The present invention relates generally to a high performance data processing system, such as a large scale digital computer, for general purpose and the like.
In the data processing system of high performance, there is adopted a highly sophisticated pipeline control system, wherein several instructions are usually executed in parallel.
What state will prevail in the data processing system upon occurrence of failure of an intermittent type or of a solid state circuit constituting the processing system is determined in dependence on a specific circuit in which the failure actually occurs and/or a particular instruction being executed. However, in the present state of technology in which the logic scale of the data processing system is more and more increased, it becomes more insufficient only to detect the circuit suffering the failure in order to determine or estimate what kinds of influences are invloved in the overall data processing system. Under the circumstances, when an apparatus serving for detection of failure and recovery of the system, referred to as a RAS (an abridgment of Reliability, Availability and Serviceability) mechanism is to be tested, it is necessary to examine or inspect the operations of the RAS mechanism by changing the condition to determine what kind of failure is caused to occur in what kind of circuit during the execution of what kind of instruction. In a data processing system, the number of circuits to be tested will be enormous. Further, since the number of instructions amounts to 100 or more, the possible instruction sequences will be numerous. Besides, even in an instruction sequence, the failure may occur in any machine cycle. Thus, the number of combinations of the testing conditions will reach astronomical figures.
In reality, since the test of all the possible combinations is impractical, those combinations which are necessary for detecting design errors and circuit errors of circuits with a relatively high failure probability are selected for the testing of the RAS mechanism.
For the test of the RAS mechanism of a data processing system there are thus required a pseudo-failure generating circuit as well as a circuit for controlling precisely the timing at which the pseudo-failure is generated. Otherwise, the test for the selected combination would not properly be carried out with useless tests being repeated, involving inefficiency in the test.
It is relatively easy to generate the pseudo-failure in a specific circuit. To this end, a scan-in circuit has been heretofore incorporated in the circuit to be tested for executing a scan-in operation for the testing. As is well known, the scan-in circuit is inherently destined to be used for the purpose of maintenance and diagnosis and provides set values in desired flip-flops which play no part in the normal operation. More specifically, the flip-flop is scanned by a pulse referred to as a scan-in timing pusle, so that the value of scan data is reflected by the state of the scanned flip-flop. Several types of scan-in systems are known. According to one of them, there is provided a scan data line independent of normal data lines, wherein the value of the scan data is set at a flip-flop of a single bit in a single scan timing, as will also be described hereinafter.
In order to insure that failure will occur in the state approximating the actual conditions of operation as closely as possible, coincidence of a predetermined address with the address of the instruction and/or the address of a microinstruction is detected to thereby trigger the activation of the scan-in circuit. This operation is referred to as the one-shot scan-in operation.
Even when the failure generating conditions are established as valid, the loading or setting of abnormal data in the circuit in which failure is caused to occur is accomplished only with a delay corresponding to 4 to 11 machine cycles due to the time required for signal transmission. As a consequence, the failure is generated only after the instruction for generating the failure has been executed, which means that the test is performed on the basis of conditions which are different from those on which the test should inherently be conducted.
Since the delay described above is not constant but varies in dependence on the packaged positions of the circuits in question, the instruction sequence to be executed must be so rearranged that execution of the instruction which involves the use of the circuit in question is effected in consideration of the applicable delay, so that the test can be performed for the combination of the instruction being executed upon occurrence of failure and the failed circuit.